Re: [SystemSafety] Static Analysis

From: GRAZEBROOK, Alvery N < >
Date: Mon, 3 Mar 2014 15:08:44 +0100

Absolutely, I agree. My point was that current practice in formal methods doesn't cross this boundary. My understanding is that you could define a formal methods process roughly as: 1. Understand the safety implications of the system and define the safety properties 2. Prove that your controller behaviour is consistent with the safety properties, for the domain where the controller can affect them.

The "wider physical world" bit happens at step 1, and only the outcome is expressed formally in the safety properties.

This interpretation covers SPARK process, and a formal process using SCADE. It could also be said to cover the application of proof checkers to VHDL in chip-design, and formal microprocessor designs or proof of properties of communication protocols. In these cases, rather than define safety properties, they select a set of correctness properties and prove those.

I would be interested in any examples where the formal verification did cross the "physical world" boundary.



-----Original Message-----
From: Michael Jackson [mailto:jacksonma_at_xxxxxx

Yes. Surely "taking the discussion on to the system behaviour applied to the wider physical world" beyond "the control / measurement systems" is what it's all about, isn't it? It's only in the wider physical world that the system purpose has meaning and the real costs of safety failures are felt.

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